  .text
  .align  2
  .global RV_sgemm_v4_block
RV_sgemm_v4_block:
  addi sp, sp, -72
  sd s7, 56(sp)
  sd s6, 48(sp)
  sd s5, 40(sp)
  sd s4, 32(sp)
  sd s3, 24(sp)
  sd s2, 16(sp)
  sd s1,  8(sp)
  sd s0,  0(sp)  
  sw a6, 64(sp)

  vsetvli t0, zero, e32, m4, ta, ma
  li s11, 4                     #循环判断所用到的值
  fcvt.s.w ft11, x0             #初始化浮点寄存器ft11==0

LOOP_An3_Bn3:
  mv s10, a5                    #重置n
  li t5, 512
  li t4, 256
  li t3, 128
  li t2, 64
  li t1, 32

  blt a4, a7, M_Less_L2  
  mv s0, a7
  sub a4, a4, a7                # - L2cache
  j LOOP_A3_Bn3
  M_Less_L2:
    blt a4, t5, M_Less_512
    li s0, 512
    addi a4, a4, -512
    j LOOP_A3_Bn3
    M_Less_512:
      blt a4, t4, M_Less_256
      li s0, 256
      addi a4, a4, -256
      j LOOP_A3_Bn3
      M_Less_256:
        blt a4, t3, M_Less_128
        li s0, 128
        addi a4, a4, -128
        j LOOP_A3_Bn3
        M_Less_128:
          blt a4, t2, M_Less_64
          li s0, 64
          addi a4, a4, -64
          j LOOP_A3_Bn3
          M_Less_64:
            blt a4, t1, M_Less_32
            li s0, 32
            addi a4, a4, -32
            j LOOP_A3_Bn3
            M_Less_32:
              li s0, 16
              addi a4, a4, -16 

LOOP_A3_Bn3:
  vsetvli t0, zero, e32, m8, ta, ma
  mv s7, a0                         #重置k
  li t5, 512
  li t4, 256
  li t3, 128
  li t2, 64
  li t1, 32

  blt s10, a7, N_Less_L2
  mv s2, a7
  sub s10, s10, a7                 
  mul t6, s0, s2                     
  j Beta_NotZero_Multiply_48_16      #一次处理32 * 32 个c元素乘法
  N_Less_L2:                        
    blt s10, t5, N_Less_512
    li s2, 512
    addi s10, s10, -512
    mul t6, s0, s2
    j Beta_NotZero_Multiply_48_16
    N_Less_512:
      blt s10, t4, N_Less_256
      li s2, 256
      addi s10, s10, -256
      mul t6, s0, s2
      j Beta_NotZero_Multiply_48_16
      N_Less_256:
        blt s10, t3, N_Less_128
        li s2, 128
        addi s10, s10, -128
        mul t6, s0, s2
        j Beta_NotZero_Multiply_48_16
        N_Less_128:
          blt s10, t2, N_Less_64
          li s2, 64
          addi s10, s10, -64
          mul t6, s0, s2               
          j Beta_NotZero_Multiply_48_16
          N_Less_64:
            blt s10, t1, N_Less_32
            li s2, 32
            addi s10, s10, -32
            mul t6, s0, s2            
            j Beta_NotZero_Multiply_32_16
            N_Less_32:
              li s2, 16
              addi s10, s10, -16
              mul t6, s0, s2                      
              j Beta_NotZero_Multiply_16_16    

Beta_NotZero_Multiply_48_16:                     
  #j Beta_NotZero_Multiply_16_16
  li t0, 768                                      #48 * 16
  rem t2, t6, t0
  bnez t2, Beta_NotZero_Multiply_32_16            
Begin_48_16:
  addi t0, a3, 128                                #1
  addi t1, a3, 256
  addi t2, a3, 384
  vle32.v v0, (a3)
  vle32.v v8, (t0)
  vle32.v v16, (t1)
  vle32.v v24, (t2)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (a3)
  vse32.v v8, (t0)
  vse32.v v16, (t1)
  vse32.v v24, (t2)
  li t1, 1024
  addi t3, a3, 512
  addi t4, a3, 640
  addi t5, a3, 768
  addi t0, a3, 896
  vle32.v v0, (t3)
  vle32.v v8, (t4)
  vle32.v v16, (t5)
  vle32.v v24, (t0)
  add a3, a3, t1
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t3)
  vse32.v v8, (t4)
  vse32.v v16, (t5)
  vse32.v v24, (t0)

  addi t0, a3, 128                                         #2
  addi t1, a3, 256
  addi t2, a3, 384
  vle32.v v0, (a3)
  vle32.v v8, (t0)
  vle32.v v16, (t1)
  vle32.v v24, (t2)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (a3)
  vse32.v v8, (t0)
  vse32.v v16, (t1)
  vse32.v v24, (t2) 
  li t1, 1024
  addi t3, a3, 512
  addi t4, a3, 640
  addi t5, a3, 768
  addi t0, a3, 896
  vle32.v v0, (t3)
  vle32.v v8, (t4)
  vle32.v v16, (t5)
  vle32.v v24, (t0)
  add a3, a3, t1
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t3)
  vse32.v v8, (t4)
  vse32.v v16, (t5)
  vse32.v v24, (t0)

  addi t6, t6, -768

  addi t0, a3, 128                                             #3
  addi t1, a3, 256
  addi t2, a3, 384
  vle32.v v0, (a3)
  vle32.v v8, (t0)
  vle32.v v16, (t1)
  vle32.v v24, (t2)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (a3)
  vse32.v v8, (t0)
  vse32.v v16, (t1)
  vse32.v v24, (t2) 
  li t1, 1024
  addi t3, a3, 512
  addi t4, a3, 640
  addi t5, a3, 768
  addi t0, a3, 896
  vle32.v v0, (t3)
  vle32.v v8, (t4)
  vle32.v v16, (t5)
  vle32.v v24, (t0)
  add a3, a3, t1
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t3)
  vse32.v v8, (t4)
  vse32.v v16, (t5)
  vse32.v v24, (t0)
  bgtz t6, Begin_48_16 
  mul t2, s0, s2                                
  mul t2, t2, s11                                
  sub a3, a3, t2                                 
  #j Beta_NotZero_Multiply_16_16
  vsetvli t0, zero, e32, m4
  j LOOP128

Beta_NotZero_Multiply_32_16:                      #循环展开 加快计算 只计算beta * c                 
  #j Beta_NotZero_Multiply_16_16
  li t1, 512                                      #32 * 16
  rem t3, t6, t1
  bnez t3, Beta_NotZero_Multiply_16_16
Begin_32_16:
  addi t0, a3, 128
  addi t1, a3, 256
  addi t2, a3, 384
  vle32.v v0, (a3)
  vle32.v v8, (t0)
  vle32.v v16, (t1)
  vle32.v v24, (t2)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1 
  vse32.v v0, (a3)
  vse32.v v8, (t0)
  vse32.v v16, (t1)
  vse32.v v24, (t2)
  
  addi t6, t6, -512

  addi t3, a3, 512
  addi t4, a3, 640
  addi t5, a3, 768
  addi t0, a3, 896
  vle32.v v0, (t3)
  vle32.v v8, (t4)
  vle32.v v16, (t5)
  vle32.v v24, (t0)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t3)
  vse32.v v8, (t4)
  vse32.v v16, (t5)
  vse32.v v24, (t0)
  
  addi t0, a3, 1024
  addi t1, a3, 1152
  addi t2, a3, 1280
  addi t3, a3, 1408
  vle32.v v0, (t0)
  vle32.v v8, (t1)
  vle32.v v16, (t2)
  vle32.v v24, (t3)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t0)
  vse32.v v8, (t1)
  vse32.v v16, (t2)
  vse32.v v24, (t3)

  li t0, 2048  
  
  addi t4, a3, 1536
  addi t5, a3, 1664
  addi t2, a3, 1792
  addi t3, a3, 1920
  vle32.v v0, (t4)
  vle32.v v8, (t5)
  vle32.v v16, (t2)
  vle32.v v24, (t3)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t4)
  vse32.v v8, (t5)
  vse32.v v16, (t2)
  vse32.v v24, (t3)

  add a3, a3, t0
  bgtz t6, Begin_32_16 
  mul t2, s0, s2                               
  mul t2, t2, s11                              
  sub a3, a3, t2                              
  vsetvli t0, zero, e32, m4
  j LOOP128

Beta_NotZero_Multiply_16_16:                      #循环展开 加快计算 只计算beta * c
  addi t0, a3, 128
  addi t1, a3, 256
  addi t2, a3, 384
  vle32.v v0, (a3)
  vle32.v v8, (t0)
  vle32.v v16, (t1)
  vle32.v v24, (t2)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (a3)
  vse32.v v8, (t0)
  vse32.v v16, (t1)
  vse32.v v24, (t2)

  addi t6, t6, -256
  li t1, 1024      #16 * 16 * 4

  addi t3, a3, 512
  addi t4, a3, 640
  addi t5, a3, 768
  addi t0, a3, 896
  vle32.v v0, (t3)
  vle32.v v8, (t4)
  vle32.v v16, (t5)
  vle32.v v24, (t0)
  vfmul.vf v0, v0, fa1
  vfmul.vf v8, v8, fa1
  vfmul.vf v16, v16, fa1
  vfmul.vf v24, v24, fa1
  vse32.v v0, (t3)
  vse32.v v8, (t4)
  vse32.v v16, (t5)
  vse32.v v24, (t0)
  
  add a3, a3, t1
  bgtz t6, Beta_NotZero_Multiply_16_16
  mul t3, s0, s2          
  mul t4, t3, s11        
  sub a3, a3, t4          #重置
  vsetvli t0, zero, e32, m4

LOOP128:                 
  mv s3, s0               
  li t0, 128             
  li t5, 112
  li t4, 96
  li t3, 80
  li t2, 64
  li t1, 48

  rem t6, s0, a6              
  bnez t6, _M_Less_L1         
  j K_Bigger_L2
  _M_Less_L1:
    blt a6, t0, L1_Less_128
    rem t6, s0, t0
    bnez t6, L1_Less_128
    j K_Bigger_L2

    L1_Less_128:
    li t0, 32
    blt a6, t5, L1_Less_112
    rem t6, s0, t5
    bnez t6, L1_Less_112          
    li a6, 112                     
    j K_Bigger_L2
    L1_Less_112:
      blt a6, t4, L1_Less_96
      rem t6, s0, t4
      bnez t6, L1_Less_96
      li a6, 96
      j K_Bigger_L2
      L1_Less_96:
        blt a6, t3, L1_Less_80
        rem t6, s0, t3
        bnez t6, L1_Less_80
        li a6, 80
        j K_Bigger_L2
        L1_Less_80:
          blt a6, t2, L1_Less_64
          rem t6, s0, t2
          bnez t6, L1_Less_64
          li a6, 64
          j K_Bigger_L2
          L1_Less_64:
            blt a6, t1, L1_Less_48
            rem t6, s0, t1
            bnez t6, L1_Less_48
            li a6, 48
            j K_Bigger_L2
            L1_Less_48:
              blt a6, t0, L1_Less_32
              rem t6, s0, t0
              bnez t6, L1_Less_32
              li a6, 32
              j K_Bigger_L2
              L1_Less_32:
                li a6, 16

K_Bigger_L2:
  li t5, 512
  li t4, 256
  li t3, 128
  li t2, 64
  li t1, 32
  li t0, 16

  blt s7, a7, K_Less_L2
  mv s1, a7
  sub s7, s7, a7                    
  j LOOP_An2_Bn2
  K_Less_L2:
    blt s7, t5, K_Less_512           
    li s1, 512
    addi s7, s7, -512
    j LOOP_An2_Bn2
    K_Less_512:
      blt s7, t4, K_Less_256
      li s1, 256
      addi s7, s7, -256
      j LOOP_An2_Bn2
      K_Less_256:
        blt s7, t3, K_Less_128
        li s1, 128
        addi s7, s7, -128
        j LOOP_An2_Bn2
        K_Less_128:
          blt s7, t2, K_Less_64
          li s1, 64
          addi s7, s7, -64
          j LOOP_An2_Bn2
          K_Less_64:
            blt s7, t1, K_Less_32
            li s1, 32
            addi s7, s7, -32
            j LOOP_An2_Bn2
            K_Less_32:
              blt s7, t0, K_Less_16
              li s1, 16
              addi s7, s7, -16
              j LOOP_An2_Bn2
              K_Less_16:
                mv s1, s7        
                li s7, 0
 
LOOP_An2_Bn2:         
  mv s4, s2            
  li t0, 128
  li t5, 112
  li t4, 96
  li t3, 80
  li t2, 64
  li t1, 48

  rem t6, s2, a6              
  bnez t6, _N_Less_L1             
  j LOOP_A2_Bn2
  _N_Less_L1:
    blt a6, t0, _N_L1_Less_128
    rem t6, s2, t0
    bnez t6, _N_L1_Less_128
    rem t6, s0, t0               
    bnez t6, _N_L1_Less_128
    #到此说明a6 = 128
    j LOOP_A2_Bn2
    _N_L1_Less_128:
      li t0, 32
      blt a6, t5, _N_L1_Less_112
      rem t6, s2, t5
      bnez t6, _N_L1_Less_112
      rem t6, s0, t5              
      bnez t6, _N_L1_Less_112
      li a6, 112
      j LOOP_A2_Bn2
      _N_L1_Less_112:
        blt a6, t4, _N_L1_Less_96
        rem t6, s2, t4
        bnez t6, _N_L1_Less_96
        rem t6, s0, t4
        bnez t6, _N_L1_Less_96
        li a6, 96
        j LOOP_A2_Bn2
        _N_L1_Less_96:
          blt a6, t3, _N_L1_Less_80
          rem t6, s2, t3
          bnez t6, _N_L1_Less_80
          rem t6, s0, t3
          bnez t6, _N_L1_Less_80
          li a6, 80
          j LOOP_A2_Bn2
          _N_L1_Less_80:
            blt a6, t2, _N_L1_Less_64
            rem t6, s2, t2
            bnez t6, _N_L1_Less_64
            rem t6, s0, t2
            bnez t6, _N_L1_Less_64
            li a6, 64
            j LOOP_A2_Bn2
            _N_L1_Less_64:
              blt a6, t1, _N_L1_Less_48
              rem t6, s2, t1
              bnez t6, _N_L1_Less_48
              rem t6, s0, t1
              bnez t6, _N_L1_Less_48
              li a6, 48
              j LOOP_A2_Bn2
              _N_L1_Less_48:
                blt a6, t0, _N_L1_Less_32
                rem t6, s2, t0
                bnez t6, _N_L1_Less_32
                rem t6, s0, t0
                bnez t6, _N_L1_Less_32
                li a6, 32
                j LOOP_A2_Bn2
                _N_L1_Less_32:
                  li a6, 16

LOOP_A2_Bn2:            
  mv s5, s1           
  li t0, 128
  li t5, 112
  li t4, 96
  li t3, 80
  li t2, 64
  li t1, 48

  rem t6, s1, a6
  bnez t6, _K_Less_L1    
  j LOOP32
  _K_Less_L1:
    blt a6, t0, _K_L1_Less_128
    rem t6, s1, t0
    bnez t6, _K_L1_Less_128
    rem t6, s2, t0
    bnez t6, _K_L1_Less_128
    rem t6, s0, t0
    bnez t6, _K_L1_Less_128
    #到此说明a6 = 128
    j LOOP32
    _K_L1_Less_128:
      li t0, 32
      blt a6, t5, _K_L1_Less_112
      rem t6, s1, t5
      bnez t6, _K_L1_Less_112
      rem t6, s2, t5
      bnez t6, _K_L1_Less_112
      rem t6, s0, t5
      bnez t6, _K_L1_Less_112
      li a6, 112
      j LOOP32
      _K_L1_Less_112:
        blt a6, t4, _K_L1_Less_96
        rem t6, s1, t4
        bnez t6, _K_L1_Less_96
        rem t6, s2, t4
        bnez t6, _K_L1_Less_96
        rem t6, s0, t4
        bnez t6, _K_L1_Less_96
        li a6, 96
        j LOOP32
        _K_L1_Less_96:
          blt a6, t3, _K_L1_Less_80
          rem t6, s1, t3
          bnez t6, _K_L1_Less_80
          rem t6, s2, t3
          bnez t6, _K_L1_Less_80
          rem t6, s0, t3
          bnez t6, _K_L1_Less_80
          li a6, 80
          j LOOP32
          _K_L1_Less_80:
            blt a6, t2, _K_L1_Less_64           
            rem t6, s1, t2
            bnez t6, _K_L1_Less_64
            rem t6, s2, t2
            bnez t6, _K_L1_Less_64
            rem t6, s0, t2
            bnez t6, _K_L1_Less_64
            li a6, 64
            j LOOP32
            _K_L1_Less_64:
              blt a6, t1, _K_L1_Less_48
              rem t6, s1, t1                     
              bnez t6, _K_L1_Less_48
              rem t6, s2, t1                     
              bnez t6, _K_L1_Less_48
              rem t6, s0, t1                     
              bnez t6, _K_L1_Less_48
              li a6, 48
              j LOOP32
              _K_L1_Less_48:
                blt a6, t0, _K_L1_Less_32
                rem t6, s1, t0
                bnez t6, _K_L1_Less_32
                rem t6, s2, t0
                bnez t6, _K_L1_Less_32
                rem t6, s0, t0
                bnez t6, _K_L1_Less_32
                li a6, 32
                j LOOP32
                _K_L1_Less_32:
                  li a6, 16                       

LOOP32:                
  mv s6, a6
  sub s5, s5, a6        
      
LOOP_An_Bn:             
  #控制__b矩阵循环
  mv s8, a6              
  addi s6, s6, -16     

LOOP_A_Bn:              
  li t0, 16
  addi s8, s8, -4       
  blt s1, t0, __K_Less_16
  mv s9, a6
  j Continue
__K_Less_16:
    mv s9, s1
Continue:
########################################################################################################
  vxor.vv v16, v16, v16 
  vxor.vv v20, v20, v20
  vxor.vv v24, v24, v24
  vxor.vv v28, v28, v28
  
  addi t0, a1, 64
  addi t1, a1, 128
  addi t2, a1, 192
 
  vle32.v v0, (a1)
  vle32.v v4, (t0)
  vle32.v v8, (t1)
  vle32.v v12, (t2)
  
  li t6, 8

  flw ft0, 0(a2)
  flw ft1, 4(a2)
  flw ft2, 8(a2)
  flw ft3, 12(a2)
  flw ft4, 16(a2)
  flw ft5, 20(a2)
  flw ft6, 24(a2)
  flw ft7, 28(a2)

  blt s1, t6, LOOP4_Corner        
  addi s9, s9, -4                

LOOP4:                            
  addi a1, a1, 256
  vfmacc.vf v16, ft0, v0
  vfmacc.vf v20, ft1, v0
  flw ft8, 32(a2)
  flw ft9, 36(a2)

  vfmacc.vf v24, ft2, v0
  vfmacc.vf v28, ft3, v0
  flw ft10, 40(a2)
  flw fa3, 44(a2)
  
  addi t3, a1, 64
  addi t4, a1, 128
  addi t5, a1, 192

  vfmacc.vf v16, ft4, v4
  vfmacc.vf v20, ft5, v4
  flw fa4, 48(a2)
  flw fa5, 52(a2) 

  vfmacc.vf v24, ft6, v4
  vfmacc.vf v28, ft7, v4
  flw fa6, 56(a2)
  flw fa7, 60(a2)
 
  vfmacc.vf v16, ft8, v8
  vfmacc.vf v20, ft9, v8
  vle32.v v0, (a1)
  
  addi a2, a2, 64

  vfmacc.vf v24, ft10, v8
  vfmacc.vf v28, fa3, v8
  vle32.v v4, (t3)

  vfmacc.vf v16, fa4, v12
  vfmacc.vf v20, fa5, v12
  flw ft0, 0(a2)
  flw ft1, 4(a2)

  vfmacc.vf v24, fa6, v12
  vfmacc.vf v28, fa7, v12
  vle32.v v8, (t4)
  vle32.v v12, (t5)
  
  addi s9, s9, -4 
  flw ft2, 8(a2)
  flw ft3, 12(a2)
  flw ft4, 16(a2)
  flw ft5, 20(a2)
  flw ft6, 24(a2)
  flw ft7, 28(a2)

  blt s9, s11, LOOP2 
  j LOOP4

LOOP2:
  vfmacc.vf v16, ft0, v0
  vfmacc.vf v20, ft1, v0
  flw ft8, 32(a2)
  flw ft9, 36(a2)

  vfmacc.vf v24, ft2, v0
  vfmacc.vf v28, ft3, v0
  flw ft10, 40(a2)
  flw fa3, 44(a2)

  vfmacc.vf v16, ft4, v4
  vfmacc.vf v20, ft5, v4
  flw fa4, 48(a2)
  flw fa5, 52(a2) 

  vfmacc.vf v24, ft6, v4
  vfmacc.vf v28, ft7, v4
  flw fa6, 56(a2)
  flw fa7, 60(a2)

  vfmacc.vf v16, ft8, v8
  vfmacc.vf v20, ft9, v8
  vfmacc.vf v24, ft10, v8
  vfmacc.vf v28, fa3, v8

  addi a1, a1, 256
  addi a2, a2, 64

  vfmacc.vf v16, fa4, v12
  vfmacc.vf v20, fa5, v12
  vfmacc.vf v24, fa6, v12
  vfmacc.vf v28, fa7, v12
  j MULTIPLY_alpha        
  
LOOP4_Corner:
  vfmacc.vf v16, ft0, v0
  vfmacc.vf v20, ft1, v0
  flw ft8, 32(a2)
  flw ft9, 36(a2)

  vfmacc.vf v24, ft2, v0
  vfmacc.vf v28, ft3, v0
  flw ft10, 40(a2)
  flw fa3, 44(a2)

  vfmacc.vf v16, ft4, v4
  vfmacc.vf v20, ft5, v4
  flw fa4, 48(a2)
  flw fa5, 52(a2) 

  vfmacc.vf v24, ft6, v4
  vfmacc.vf v28, ft7, v4
  flw fa6, 56(a2)
  flw fa7, 60(a2)

  addi a1, a1, 256
  addi a2, a2, 64

  vfmacc.vf v16, ft8, v8
  vfmacc.vf v20, ft9, v8
  vfmacc.vf v24, ft10, v8
  vfmacc.vf v28, fa3, v8

  vfmacc.vf v16, fa4, v12
  vfmacc.vf v20, fa5, v12
  vfmacc.vf v24, fa6, v12
  vfmacc.vf v28, fa7, v12  
############################################################################################
MULTIPLY_alpha:
  vsetvli t0, zero, e32, m8      #混合寄存器长度
  vfmul.vf v16, v16, fa0
  vfmul.vf v24, v24, fa0
  
Beta_NotZero_Add:
  addi t1, a3, 128
  vle32.v v0, (a3)
  vfadd.vv v16, v16, v0
  vse32.v v16, (a3)

  vle32.v v8, (t1)
  vfadd.vv v24, v24, v8
  vse32.v v24, (t1) 
  addi a3, a3, 256    

End_One:
  li t2, 16
  vsetvli t0, zero, e32, m4
  li t1, 64           # 16 * 4
  blt s1, t2, K_Edge_Less16
  mul t0, t1, a6
  sub a1, a1, t0     
  bgtz s8, LOOP_A_Bn
 
  add a1, a1, t0     
  mul t2, a6, a6
  mul t2, t2, s11    
  sub a2, a2, t2     
  bgtz s6, LOOP_An_Bn   
 
  add a2, a2, t2     
  sub a3, a3, t2         
  bgtz s5, LOOP32
  
  sub s4, s4, a6
  mul t1, a6, a6
  mul t1, t1, s11     
  add a3, a3, t1      
  mul t2, s1, a6      
  mul t2, t2, s11
  sub a1, a1, t2     
  bgtz s4, LOOP_A2_Bn2
    
  sub s3, s3, a6      #控制循环
  add a1, a1, t2     
  mul t3, s1, s2   
  mul t3, t3, s11    
  sub a2, a2, t3   
  bgtz s3, LOOP_An2_Bn2

  mul t2, s0, s2      
  mul t2, t2, s11   
  sub a3, a3, t2
  add a2, a2, t3      
  bgtz s7, LOOP128
 
  lw a6, 64(sp)
  add a3, a3, t2      
  mul t3, s0, a0       
  mul t3, t3, s11      
  sub a1, a1, t3       
  bgtz s10, LOOP_A3_Bn3
  
  add a1, a1, t3      
  mul t4, a0, a5       
  mul t4, t4, s11
  sub a2, a2, t4      
  bgtz a4, LOOP_An3_Bn3
  j End_All
 
K_Edge_Less16:
  mul t0, t1, s1       
  sub a1, a1, t0       
  bgtz s8, LOOP_A_Bn

  add a1, a1, t0      
  mul t2, a6, s1
  mul t2, t2, s11    
  sub a2, a2, t2    
  bgtz s6, LOOP_An_Bn

  mul t2, a6, s1
  mul t2, t2, s11
  add a2, a2, t2     
  mul t1, a6, a6
  mul t1, t1, s11
  sub a3, a3, t1     
  bgtz s5, LOOP32

  sub s4, s4, a6            
  add a3, a3, t1
  mul t2, s1, a6     
  mul t2, t2, s11
  sub a1, a1, t2
  bgtz s4, LOOP_A2_Bn2

  sub s3, s3, a6     
  add a1, a1, t2      
  mul t3, s1, s2     
  mul t3, t3, s11    
  sub a2, a2, t3      # 回退
  bgtz s3, LOOP_An2_Bn2

  mul t2, s0, s2     
  mul t2, t2, s11   
  sub a3, a3, t2
  add a2, a2, t3     
  bgtz s7, LOOP128

  lw a6, 64(sp)
  add a3, a3, t2     
  mul t3, s0, a0      
  mul t3, t3, s11      
  sub a1, a1, t3      
  bgtz s10, LOOP_A3_Bn3

  add a1, a1, t3       #更新_a地址
  mul t4, a0, a5       #k * n *4
  mul t4, t4, s11
  sub a2, a2, t4       #重置b地址
  bgtz a4, LOOP_An3_Bn3

End_All:
  ld s7, 56(sp)
  ld s6, 48(sp)
  ld s5, 40(sp)
  ld s4, 32(sp)
  ld s3, 24(sp)
  ld s2, 16(sp)
  ld s1,  8(sp)
  ld s0,  0(sp)
  addi sp, sp, 72
ret